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74AC273 * 74ACT273 Octal D-Type Flip-Flop
November 1988 Revised March 2005
74AC273 * 74ACT273 Octal D-Type Flip-Flop
General Description
The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
s Ideal buffer for microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous master reset s See 377 for clock enable version s See 373 for transparent latch version s See 374 for 3-STATE version s Outputs source/sink 24 mA s 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number 74AC273SC 74AC273SJ 74AC273MTC 74AC273PC 74ACT273SC 74ACT273SJ 74ACT273MTC 74ACT273MTCX_NL (Note 1) 74ACT273PC Package Number M20B M20D MTC20 N20A M20B M20D MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009954
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74AC273 * 74ACT273
Connection Diagram
Pin Descriptions
Pin Names D0-D7 MR CP Q0-Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs
Mode Select-Function Table Logic Symbols
Inputs Operating Mode MR Reset (Clear) Load `1' Load `0'
H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition
Outputs Dn X H L Qn L H L
CP
L H H

X
IEEE/IEC
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC273 * 74ACT273
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r 50 mA r 50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V for AC Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V for ACT 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) (PDIP)
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 5.5 5.5 5.5 4.0 75 mA mA VOLD VOHD VIN or GND 1.65V Max 3.85V Min VCC 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1 V V
IOH IOH IOH IOUT VIN
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND
0.44 0.44 0.44 V
IOL IOL IOL VI
r0.1
r1.0
PA
75
40.0
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC273 * 74ACT273
AC Electrical Characteristics for AC
VCC Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay Clock to Output Propagation Delay MR to Output
Note 6: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 90 140 4.0 3.0 4.0 3.0 4.0 3.0
25qC
50 pF Typ 125 175 7.0 5.5 7.0 5.0 7.0 5.0 12.5 9.0 13.0 10.0 13.0 10.0 Max
TA
40qC to 85qC
CL 50 pF Max MHz 14.0 10.0 14.5 11.0 14.0 10.5 ns ns ns Units
(V) (Note 6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Min 75 125 3.0 2.5 3.5 2.5 3.5 2.5
AC Operating Requirements for AC
VCC Symbol Parameter (V) (Note 7) tS Setup Time, HIGH or LOW Data to CP tH Hold Time, HIGH or LOW Data to CP tW Clock Pulse Width HIGH or LOW tW MR Pulse Width HIGH or LOW trec Recovery Time MR to CP
Note 7: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 3.5 2.5
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 5.5 4.0 0 1.0 5.5 4.0 5.5 4.0 3.5 2.0 6.0 ns 4.5 0 ns 1.0 6.0 ns 4.5 6.0 ns 4.5 4.5 ns 3.0
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
2.0 1.0
3.5 2.5 2.0 1.5 1.5 1.0
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74AC273 * 74ACT273
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 9) Maximum Quiescent Supply Current
Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 4.49 5.49
25qC
2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V IOUT VIN
50 PA
VIL or VIH
V
IOH IOH
24 mA 24 mA (Note 8)
50 PA VIL or VIH 24 mA 24 mA (Note 8) VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC
0.001 0.001
0.1 0.1 0.36 0.36
V
IOUT VIN
V
IOL IOL
5.5 5.5 5.5 5.5 5.5 0.6
r0.1
r1.0
1.5 75
PA
mA mA mA
VI VI
VOLD VOHD VIN or GND
75
4.0 40.0
PA
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 10) fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 125 1.5 1.5
25qC
50 pF Typ 189 6.5 7.0 8.5 9.0 Max
TA
40qC to 85qC
CL 50 pF Max MHz 9.0 8.5 ns ns Units
Min 110 1.5 1.5
2.0 5.0 5.0
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74AC273 * 74ACT273
AC Operating Requirements for ACT
VCC Symbol Parameter (V) (Note 11) tS Setup Time, HIGH or LOW 5.0 Dn to CP tH Hold Time, HIGH or LOW 5.0 Dn to CP tW Clock Pulse Width 5.0 HIGH or LOW tW MR Pulse Width 5.0 HIGH or LOW tW Recovery Time 5.0 MR to CP
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 1.0
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 3.5 3.5 ns
0.5
1.5
1.5
ns
2.0
4.0
4.0
ns
1.5
4.0
4.0
ns
0.5
3.0
3.0
ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance for AC Power Dissipation Capacitance for ACT Typ 4.5 50.0 40.0 Units pF pF Conditions VCC VCC OPEN 5.0V
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74AC273 * 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC273 * 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74AC273 * 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74AC273 * 74ACT273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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